NATHAN PETERSON

8125B Ceberry Drive . Austin, Texas 78759 . Phone (512) 484-3758

PROFILE

Highly motivated engineer with nearly seven years of chip design experience including circuit design, logic design, and specializing in hierarchical static timing analysis and timing methodology. Successfully brought multiple chips through design cycle as chip timing lead. Especially skilled at scripting and debugging problems. Expert at Perl programming and proficient with Tcl, Ksh, and other languages.

TECHNICAL SUMMARY

EXPERIENCE

Programmer / Technical Expert, Nathan Peterson Consulting 2006 - Present

• Found the crucial information for a winning lawsuit case by characterizing ms-olap transactions via TCP/IP network packet sniffing as a technical expert for Tipton Cole and Co.
• Performed 68k microcontroller machine code analysis for Tipton Cole and Co.
• Reverse engineered the authentication mechanism for a proprietary instant messaging protocol and implemented a plugin for a cross-platform instant messaging client in object oriented c.

Chip Designer / Timing Engineer, IBM 2000 - 2006

• Power 6 / zSeries z6:
• Successfully brought chip to tape out as chip timing lead. Responsibilities: setting up and maintaining timing scripts / assertion files, executing massive nightly timing runs, driving timing fixes, holding weekly timing takedown meetings, ensuring proper/accurate deliverables from designers, presenting timing status, ensuring accurate/useful timing information is available to designers, and maintaining tapeout timing criteria.
• Interacted with integration/logic/circuit/timing teams across multiple sites to ensure successful timing takedown on multiple projects.
• Stepped up to handle integration solutions for all of the timing critical buses at the chip-level that passed through multiple levels of hierarchy and relived management concern by designing a methodology for organizing, tracking, analyzing, and fixing fails on these nets, as well as creating and successfully executing a plan of attack for a 6 month schedule to tape out.
• Designed and implemented logic for second generation on-chip wire testing macro for hardware noise analysis.
• Led timing takedown on a flat chip-level unit with a 1.5x clock domain interacting with 1x, 3x, and async clock domains.
• Worked on timing methodology and memory/runtime performance issues for timing tools. Worked with EDA team and AIX performance team to resolve critical issues.
• Wrote essential scripts used in timing process which are now used in multiple projects.
• Power 5:
• Successfully brought chip through multiple tape outs as chip timing lead.
• Developed and managed skill code for automated block and buffering placement/connections for a flat chip-level unit.
• Successfully brought a chip-level unit through multiple tape outs as unit timing lead.
• Synthesized various macros in a chip-level unit as well as developed scripting for custom manual/automated early mode buffering methodology.
• Maintained VHDL releases and verification statistics for a chip-level unit as well as made VHDL fixes, bus connections and wrote code for optimal updating of scan chain connections.
• Wrote VHDL for, and tested in lab, an innovative on-chip wire testing macro for hardware noise analysis.
• Implemented and maintained circuits as well as custom layout fixes for 20 custom macros. This involved initial abstract sizing and abstract generation, circuit implementation from RTL, device sizing, spice analysis, monitoring and implementing timing/logic/DFT/power fixes, RC extraction, timing and noise rule generation, and running various checks such as LVS, DRC, meth, electrical, yield, and formal verification.
• Wrote VHDL for various bug and performance fixes for register mapping in the Instruction Sequencing Unit.
• PowerPC 970:
• Led timing takedown on a core-level unit.
• Analyzed existing logic for clockgating and powersavings potential and implemented the VHDL changes.
• Implemented and maintained circuits for 25 custom macros.
• Power 4:
• Designed the verification infrastructure for the Instruction Sequencing Unit arrays using Verilog behavioral modeling.
• Managed circuits for 20 custom macros.
• Created block diagram documentation for all of the register mapping functionality in the Instruction Sequencing Unit.

ADDITIONAL PROGRAMMING EXPERIENCE

• Wrote a juggling animation program and mathematical juggling notation generator for the palm pilot in c called SiteSwap.
• Wrote an ncurses front end for an eastern orthodox text editor in c.
• Wrote a hi-res breakout game with advanced powerup features and level editor in x86 assembly.
• Wrote code for Mozilla Thunderbird.
• Reverse-engineered the protocol for the original Philips Streamium MCi-200 Internet Stereo and implemented a custom cross-platform server via perl scripting (mentioned on Slashdot.org).

EDUCATION

University of Illinois at Urbana-Champaign, BS, Electrical Engineering

Awards:

• National Dean's List
• VTC Scholarship
• HKN Engineering honors society